256-channel, 24-bit current-to-digital adc module data sheet ADAS1131 rev. sp0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2014 analog devices, inc. all rights reserved. technical support www.analog.com features 256-channel, current-to-digital converter module up to 24-bit resolution variable integration time fastest integration time: 11.656 ksps (86 s) at 20-bit resolution low power dissipation: 3 mw per channel at any throughput integral linearity 0.015% of reading 0.4 ppm of fsr: single channel active 0.050% of reading 1.0 ppm of fsr: all channels active very low noise simultaneous sampling no dead time, no loss of charge, 100% charge collection user adjustable full-scale range on-board temperature sensor and reference buffer 15 mm 15 mm, csp_bga package simple printed circuit board (pcb) design integrated capacitors for supply and reference decoupling 0.80 mm pitch bga allows low cost pcb technology support tools evaluation board reference design with reference layout fpga verilog code applications medical, industrial, and security ct scanner data acquisition photodiode sensors dosimetry and radiation therapy systems optical fiber power monitoring x-ray detection systems high channel-count data acquisition systems (current or voltage inputs) general description the ADAS1131 is a 256-channel, current-to-digital analog-to- digital converter (adc) module. it contains 256 low power, low noise, low input current integrators, simultaneous sample-and- holds, and two high speed, high resolution adcs with configurable sampling rate and resolutions of up to 24 bits. the signal chain and sampling architecture of the ADAS1131 is designed to guarantee that all channels are simultaneously sampled, and that no charge is lost throughout the sampling process. all converted channel results are output on a single, low voltage differential signaling (lvds), self clocked serial interface, which reduces external hardware. an spi-compatible serial interface allows configuration of the adc using the sdi_x input. the sdo_x output allows the user to daisy-chain several adcs on a single, 3-wire bus. the ADAS1131 uses the separate supply, iovdd, to reduce digital noise effect on the conversions. the ADAS1131 is in a 15 mm 15 mm, csp_bga package. functional block diagram figure 1. for more information about the ADAS1131 , email adas@analog.com . f s/h f s/h adcl + ? an0 an127 f s/h f s/h adch + ? an128 an255 kgnd vt_x data processing lvds/cmos interface temperature ADAS1131 2.5v vdd2 1.8v vdd1 3.3v vdd3 to next sdi sdi sdo_x ref 2.048v sdi_x from previous sdo sdi ref configuration sck cs_x doutx_x clkx sync iovdd reset gnd to all adcs 2.5v from dout of other adcs fpga vio 12360-001
ADAS1131 data sheet rev. sp0 | page 2 of 2 notes ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12360f-0-7/14(sp0)
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